1. Field of the Invention
The present invention is related to a multiplication circuit used for a high speed multiplier in a computer system.
2. Description of the Related Art
As is well known, multiplication of binary numbers is performed by repeating addition and carry in the multiplier of the computer system. Also, as is well known, there are two methods of binary number multiplication, i.e., one, a parallel arithmetic method using an array circuit arrangement; and two, a carry save adder (CSA) tree method using a plurality of carry save adders, each connected branchwise.
In the CSA three method, many gate circuits are used for performing multiplication in the CSA trees. However, the more gate circuits included, the longer the operation time, so that high speed operation is impeded in the multiplication circuit. This problem is explained in detail hereinafter.